Device and method for protecting gate terminal and lead

ABSTRACT

A resist region covering the gate terminal and lead of the gate electrode line and between a passivation layer and a gate insulating layer is used to protect the gate terminal and lead. The resist region is located at a scribing line on margin of the color filter substrate of a panel, thereby the resist region can protect the passivation layer and the gate insulating layer from cracking, and the gate terminal and the lead from corrosion after a portion of the color filter substrate is removed along the scribing line.

BACKGROUND

1. Field of the Invention

The present invention generally relates to a device and method forprotecting gate terminal and lead, and more particularly to a device andmethod for protecting gate terminal and lead at stage of scribing andspalling.

2. Description of the Prior Art

In fabrication of thin film transistor (TFT) liquid crystal display(LCD) device, an array substrate and a color filter substrate areprovided respectively, in which thin film transistor array on the arraysubstrate are formed by thin film deposition, lithographic process, andetching step of semiconductor process. Having been formed the twosubstrates, an assembling process, a scribing step, and a spalling stepare performed. The scribing and spalling steps are to remove peripheralregions on the color filter substrate such that contact plugs of gateterminals on the array substrate can be exposed.

The scribing and spalling steps can be shown in FIG. 1, wherein adisplay region on an array substrate 100 includes a thin film transistorand a peripheral region includes a gate line 102. The thin filmtransistor, covered and protected by a passivation layer 112, has a gate102, gate insulating layer 104, island semiconductor layer 106, andsource/drain 108. A contact plug 114 on gate terminal of the gate line102 is used to connect driver IC electrically. Another substrate 130,which is also called color filter substrate, has a black matrix on theinner side and assembled with the array substrate 100. In the TFT-LCDfabricating process, after the two substrates are assembled, thescribing and spalling steps are performed. In FIG. 1, scribing line isdenoted by dash line, and the contact plug 114 is exposed afterscribing.

However, material of the gate insulating layer 104 and the passivationlayer 112 is silicon nitride, which has less strain at the stage ofscribing and spalling steps to break the two layers. Further, after thegate insulating layer 104 and the passivation layer 112 are broken, gasor origin of pollution will reach the gate line 102 along splits to makethe gate terminal of gate line 102 corrosion or oxidation. This willcause the display panel fail. Therefore, a solution for resolving issuescaused at the scribing and spalling steps is necessary.

SUMMARY

In accordance with the present invention, a resist region between thepassivation and the gate insulating layer on the array substrate isprovided. When the panel is scribed and spalled, the resist region canprovide sufficient strain to protect the gate insulating layer andpassivation layer from breaking.

It is another object of this invention to provide a less activity resistregion compared to the gate terminal and lead of gate line to preventgate line from corrosion.

It is a further object of this invention to have a floating resistregion such that there is no electrical connection between the resistregion and any circuit of the display panel.

It is still another object of this invention that formation of theresist region can be combined to the present TFT fabrication processwithout increasing TFT fabrication cycle time.

In one embodiment, a device for protecting a gate terminal and lead atstage of scribing and spalling a LCD panel is provided, wherein the LCDpanel comprises a first substrate with thin film transistor arraythereon and a second substrate thereon within color filter opposite tothe thin film transistor array. The device comprises a resist regioncovering the gate terminal and lead of the gate electrode line andbetween a passivation layer and a gate insulating layer, and located ata scribing line on margin of the second substrate of the panel, therebythe resist region can protect the passivation layer, and the gateinsulating layer from cracking, the gate terminal and lead fromcorrosion after a portion of the second substrate is removed along thescribing line.

A method for protecting a gate terminal and lead at stage of scribingand spalling a LCD panel is also provided. The method comprises steps offorming the gate electrode and the gate electrode line on a firstsubstrate, wherein the first substrate is also called array substrate orlower substrate, and the gate electrode line comprises the gate terminaland the lead. Then, a blanket gate insulating layer is deposited on thegate electrode, the gate electrode line, and the substrate. Next, anisland semiconductor layer is formed on the gate electrode and a sourceelectrode and a drain electrode on the island semiconductor layer, and aresist region is simultaneously formed on the gate insulating layer andcovering the gate terminal and the lead of a gate electrode line,wherein the resist region is located at a scribing line on margin of asecond substrate with color filter thereon. Afterward, a blanketpassivation layer is deposited on the source electrode, the drainelectrode, and the resist region thereby the resist region can protectthe passivation layer, and the gate insulating layer from cracking, thegate terminal and the lead from corrosion after a portion of the secondsubstrate is removed along the scribing line.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of thisinvention will become more readily appreciated as the same becomesbetter understood by reference to the following detailed description,when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 illustrates a schematic representation of an LCD panel at thestage of scribing and spalling by using conventional method whereinpassivation layer, gate insulating layer, gate terminal as well as leadof gate line on array substrate may be damaged;

FIG. 2 illustrates a schematic representation of a method in accordancewith this invention wherein gate electrode and gate line are formed onan array substrate with a gate insulating layer thereon;

FIG. 3 illustrates a schematic representation of a method in accordancewith this invention wherein a thin film transistor is formed on thearray substrate and a resist region is formed on the gate insulatinglayer;

FIG. 4 illustrates a schematic representation of a method in accordancewith this invention wherein a passivation layer is formed on the thinfilm transistor and a contact window is formed on the gate terminal;

FIG. 5 illustrates a schematic representation of a method in accordancewith this invention wherein the resist layer can protect passivationlayer, gate insulating layer, and gate terminal as well as lead of gateline on the array substrate at the stage of scribing and spalling; and

FIG. 6 illustrates a top view of the resist region on the gate terminaland lead in accordance with this invention.

DETAILED DESCRIPTION

Some sample embodiments of the present invention will now be describedin greater detail. Nevertheless, it should be recognized that thepresent invention can be practiced in a wide range of other embodimentsbesides those explicitly described, and the scope of the presentinvention is expressly not limited except as specified in theaccompanying claims.

This invention provides a device for protecting a gate terminal and leadat stage of scribing and spalling a LCD panel, wherein the LCD panelcomprises a first substrate with thin film transistor array thereon anda second substrate thereon within color filter opposite to the thin filmtransistor array. The device comprises a resist region covering the gateterminal and lead of gate electrode line and between a passivation layerand a gate insulating layer, and located at a scribing line on margin ofthe second substrate of the panel, thereby the resist region can protectthe passivation layer and the gate insulating layer from cracking, thegate terminal and lead from corrosion after a portion of the secondsubstrate is removed along the scribing line. Material of the resistregion is metal and the resist region is floating between the gateinsulating layer and the passivation layer. Activity of the resistregion is less than the gate electrode line.

Distance between the scribing line and margin of the resist region isabout more than 50 μm, and width of the resist region is larger than thegate terminal and the gate electrode line.

Material of the resist region can be the same as source/drain electrodesof the thin film transistor, and step of formation the resist region isat a step of formation of the source/drain electrodes, wherein formationof the resist region comprises steps of providing the first substratewith a gate electrode and the gate electrode line thereon, and the gateinsulating layer covering the gate electrode, the gate electrode line,and the array substrate, wherein the first substrate is also calledarray substrate or lower substrate. Then, an island semiconductor layeris formed on the gate insulating layer and over the gate electrode.Next, a blanket metal layer is deposited on the island semiconductorlayer and the gate insulating layer. A lithographic process is thenperformed to the conductive layer by using a reticle with a sourcepattern and a drain pattern on the gate electrode and a resist regionpattern on the gate terminal and lead. Afterward, the conductive layeris etched to form the source/drain electrodes and the resist region.

Material of the resist region can be the same as island semiconductorlayer of the thin film transistor, and step of formation the resistregion is at the step of formation of the island semiconductor layer,wherein formation of the resist region comprises steps of providing thefirst substrate with a gate electrode and the gate electrode linethereon, the gate insulating layer blanket on the gate electrode, thegate electrode line wherein the first substrate is also called arraysubstrate or lower substrate, and the array substrate. Then, a blanketsemiconductor layer is deposited on the gate insulating layer. Next, alithographic process is performed to the semiconductor layer by using areticle with an island pattern on the gate electrode and a resist regionpattern on the gate terminal and the lead. Afterward, the semiconductorlayer is etched to form the island semiconductor layer and the resistregion.

This invention also provides a method for protecting a gate terminal andlead at stage of scribing and spalling a LCD panel. The method comprisessteps of forming the gate electrode and the gate electrode line on afirst substrate, wherein the first substrate is also called arraysubstrate or lower substrate, and the gate electrode line comprises thegate terminal and the lead. Then, a blanket gate insulating layer isdeposited on the gate electrode, the gate electrode line, and thesubstrate. Next, an island semiconductor layer is formed on the gateelectrode and a source electrode and a drain electrode on the islandsemiconductor layer, and a resist region is simultaneously formed on thegate insulating layer and covering the gate terminal and the lead of thegate electrode line, wherein the resist region is located at a scribingline on margin of a second substrate with color filter thereon. Materialof the resist region is metal and the resist region is floating betweenthe gate insulating layer and the passivation layer. Activity of theresist region is less than the gate electrode line. Distance between thescribing line and margin of the resist region is about more than 50 um,and width of the resist region is larger than the gate terminal and thegate electrode line. Afterward, a blanket passivation layer is depositedon the source electrode, the drain electrode, and the resist regionthereby the resist region can protect the passivation layer and the gateinsulating layer from cracking, the gate terminal and the lead fromcorrosion after a portion of the second substrate is removed along thescribing line.

Material of the resist region can be the same as source/drain electrodesof the thin film transistor, and step of formation the resist region isat a step of formation of the source/drain electrodes. Formation of theresist region comprises steps of forming an island semiconductor layeron the gate insulating layer and over the gate electrode. Then, ablanket metal layer is deposited on the island semiconductor layer andthe gate insulating layer. Next, a lithographic process is performed tothe conductive layer by using a reticle with a source pattern and adrain pattern on the gate electrode and a resist region pattern on thegate terminal and the lead. Afterward, the conductive layer is etched toform the source electrode, the drain electrode and the floating metalresist region.

One embodiment is disclosed according to this invention. Referring toFIG. 2, a gate electrode 12 (at right hand side display region) and agate line 12(at left hand side display region) are formed on a firstsubstrate 10, and a blanket gate insulating layer 14 is formed on thegate electrode 12, gate line 12, and first substrate. The firstsubstrate 10 is also called array substrate or lower substrate of LCDpanel. When a back light source is used as light source for liquidcrystal display device, the first substrate 10 is transparent, such asglass or transparent plastic. When a front light source is used as lightsource of the display device, the first substrate 10 should notnecessary be transparent. Material of the gate electrode layer 12 can bemetal or any kind of conductive material, such as aluminum or aluminumalloy, molybdenum or molybdenum tungsten alloy, chromium or tantalum.Formation of the gate electrode layer 12 is to deposit a conductivelayer by using sputtering method on the first substrate 10, andlithographic and etching processes are performed to form a gateelectrode pattern on a predetermined position. When gate electrodepattern is formed on the first substrate 10, gate line 12 is also formedon the first substrate 10. The gate line 12 includes gate terminal andlead, which always at one margin of the display panel. The gate line andgate electrode 12 are formed at one step and have the same material.

A blanket insulating layer 14 is formed on the first substrate 10 tocover the gate electrode and the gate line 12. The insulating layer 14,also called gate insulating layer, material of which is silicon nitride,is a blanket deposited on the gate electrode and the gate line 12 andfirst substrate 10. The insulating layer 14 serves as the gatedielectric layer of the thin film transistor and provides insulateisolation on the other area. Formation of the insulating layer 14 usespopular chemical vapor deposition method.

Referring to FIG. 3, a thin film transistor is formed on display regionand a resist region 20 is formed on the peripheral region. Formation ofthe thin film transistor is to form the island semiconductor layer 16and metal source/drain 18. Material of the resist region 20 may be thesame as metal source/drain 18, island semiconductor 16, or a compositelayer including both semiconductor layer and metal layer. Position ofthe resist region 20 is about on scribing line when the display panel isassembled and scribed, in which distance between the scribing line andboth ends of the resist region 20 is about more than 50 μm, and width ofthe resist region is larger than the gate terminal and lead. Activity ofpreferred material of the resist region 20 is less than the gate line12, because the gate line 12 will be corroded or oxidized after theresist region 20 is completely eroded or oxidized when both thepassivation layer 22 and the gate insulating layer 14 are crack. Theless activity of the resist region 20 is the longer duration of resistregion 20 is eroded or oxidized, and possibility of gate line 12 erodingor oxidizing can be decreased. The resist region 20 is floating betweenthe passivation layer 22 and the gate insulating layer 14 and do notconnect electrically with other conductivity or semiconductor.

Formation of the resist region 20 can have many ways. One method is touse material of metal source/drain 18 for the resist region 20. Themethod is to form an island semiconductor layer 16 on the insulatinglayer 14 and over the gate electrode layer 12. The semiconductor layer16 primarily provides a channel region of the thin film transistor. Inthin film transistor-liquid crystal display device, channel region isabove the gate electrode layer 12, and also named back channel region.The semiconductor layer 16 uses a composite layer within double layers,which is underneath amorphous silicon layer and upper n-doped amorphoussilicon layer. The underneath amorphous silicon layer provides channelregion of the transistor, while the upper n-doped amorphous siliconlayer serves as ohmic contact between metal and semiconductor to reduceresistance between metal source/drain and semiconductor layer.

A conductive layer 18, served as source and drain electrodes, are formedon the island semiconductor layer 16, and a thin film transistor istherefore formed. Material of this conductive layer 18 can be aluminumor aluminum alloy, molybdenum or molybdenum tungsten alloy, chromium ortantalum. Formation of the source and drain electrodes is to deposit ablanket conductive layer on the island semiconductor layer 16 and thegate insulating layer 14, and then a lithographic process is performedto remove a portion of conductive layer 18 to leave the source and drainelectrodes. In this lithographic process, there is a resist pattern onperipheral of the reticle, and the resist region 20 is formed after thefollowing etching step.

Another method is to form the resist region 20 simultaneously when theisland semiconductor layer 16 is formed. The method is to form a blanketsemiconductor layer on the gate insulating layer 14. Then, alithographic process and an etching step are performed to form an islandsemiconductor layer 16 over the gate electrode 12. In this lithographicprocess, there is a resist pattern on peripheral of the reticle, and theresist region 20 is formed after the etching step.

A further method is to comply with the current 4 lithographic processes,which means formation of the island semiconductor layer and thesource/drain utilize one lithographic process. A blanket semiconductorlayer and a blanket metal layer are deposited sequentially on the gateinsulating layer 14. Then, a lithographic process and an etching stepare performed to form an island semiconductor layer 16 over the gateelectrode 12 and a metal source/drain 18 thereon. In this lithographicprocess, there is a resist pattern on peripheral of the reticle, and theresist region 20 is formed after the etching step.

Referring to FIG. 4, a blanket passivation layer 22 is formed on thethin film transistor, the resist region 20 and the gate insulating layer14. The passivation layer 22 can be silicon nitride and formed bychemical vapor deposition method. Then, another lithographic process andan etching step are performed to form contact windows for drainelectrode and the terminals on the peripheral of display panel. Thecontact plug 24 in FIG. 4 uses transparent conductive layer, andformation of the contact plug 24 can be combined to formation of thetransparent conductive electrode. After the passivation layer 22 isformed, the resist region 20 is floating.

Referring to FIG. 5, a second substrate 30, which is also called colorfilter substrate, is assembled to the array substrate 10 and scribed andspalled, wherein the dash line indicates scribing line. Inner side ofthe color substrate 30 has a black matrix 32 opposite to the array inthe figure. When the color filter substrate 30 is cut along the scribingline to remove the peripheral region, the resist region 20 providessufficient stress for array substrate 10 to protect passivation layer 22and gate insulating layer 14 from cracking. Even if the passivationlayer 22 and gate insulating layer 14 is broken, eroding or oxidizingrate of the gate line 12 can be postponed due to activity of the resistregion 20 is less than the gate line 12. After the scribing and spallingsteps, contact plug 24 on the gate terminal is exposed, and will connectto driver IC on flexible printed circuit board electrically.

Referring to FIG. 6, a top view of the resist region 20 is shown. Widthof the resist region 20 is larger than gate terminal and lead, anddistance between the scribing line and both ends of the resist region 20is about more than 50 μm. Such kind of dimension will provide betterstrain.

This invention provides a resist region between the passivation and thegate insulating layer on the array substrate. When the panel is scribedand spalled, the resist region can provide sufficient strain to protectthe gate insulating layer and passivation layer from breaking. Moreover,this invention provides a less activity of the resist region compared tothe gate terminal and lead of gate line to prevent gate line fromcorrosion or oxidization, and has a floating resist region such thatthere is no electrical connection between the resist region and anycircuit of the display panel. Further, formation of the resist regioncan be combined to the present TFT fabrication process withoutincreasing TFT fabrication cycle time.

Although specific embodiments have been illustrated and described, itwill be obvious to those skilled in the art that various modificationsmay be made without departing from what is intended to be limited solelyby the appended claims.

From the foregoing, it will be appreciated that specific embodiments ofthe invention have been described herein for purposes of illustration,but that various modifications may be made without deviating from thespirit and scope of the invention. Accordingly, the invention is notlimited except as by the appended claims.

1. A device for protecting a gate terminal and lead of a gate electrodeline at stage of scribing and spalling a liquid crystal display panel,said liquid crystal display panel comprising a first substrate with thinfilm transistor array thereon and a second substrate thereon with colorfilter opposite to said thin film transistor array, said devicecomprising: a resist region covering said gate terminal and said lead ofthe gate electrode line and between a passivation layer and a gateinsulating layer, said resist region located at a scribing line onmargin of the second substrate of the panel.
 2. The device according toclaim 1, wherein material of said resist region is metal.
 3. The deviceaccording to claim 2, wherein said resist region is a floating region.4. The device according to claim 2, wherein material of said resistregion is the same as source/drain electrodes of the thin filmtransistor.
 5. The device according to claim 4, wherein said resistregion is formed by a step of said source/drain electrodes.
 6. Thedevice according to claim 5, wherein said resist region is formed bysteps comprising: providing said array substrate with a gate electrodeand said gate electrode line thereon, and said gate insulating layercovering said gate electrode, said gate electrode line, and said arraysubstrate; forming an island semiconductor layer on said gate insulatinglayer and over said gate electrode; depositing a blanket metal layer onsaid island semiconductor layer and said gate insulating layer;performing a lithographic process to said conductive layer by using areticle with a source pattern and a drain pattern on said gate electrodeand a resist region pattern on said gate terminal and said lead; andetching said conductive layer to form said source/drain electrodes andsaid resist region.
 7. The device according to claim 1, wherein materialof said resist region is the same as island semiconductor layer of thethin film transistor.
 8. The device according to claim 7, wherein saidresist region is formed by a step of formation of said islandsemiconductor layer.
 9. The device according to claim 8, wherein saidresist region is formed by steps comprising: providing said arraysubstrate with a gate electrode and said gate electrode line thereon,said gate insulating layer blanket on said gate electrode, said gateelectrode line, and said array substrate; depositing a blanketsemiconductor layer on said gate insulating layer; performing alithographic process to said semiconductor layer by using a reticle withan island pattern on said gate electrode and a resist region pattern onsaid gate terminal and said lead; and etching said semiconductor layerto form said island semiconductor layer and said resist region.
 10. Thedevice according to claim 1, wherein activity of said resist region isless than said gate electrode line.
 11. The device according to claim 1,wherein distance between said scribing line and margin of said resistregion is about more than 50 μm.
 12. The device according to claim 11,wherein width of said resist region is larger than said gate terminaland said gate electrode line.
 13. A method for protecting a gateterminal and lead at stage of scribing and spalling a liquid crystalpanel, said method comprising: providing a first substrate; forming thegate electrode and the gate electrode line on said first substrate,wherein said gate electrode line comprises said gate terminal and saidlead; depositing a blanket gate insulating layer on said gate electrode,said gate electrode line, and said substrate; forming an islandsemiconductor layer on said gate electrode and a source electrode and adrain electrode on said island semiconductor layer, and simultaneouslyforming a resist region on said gate insulating layer and covering saidgate terminal and said lead of a gate electrode line, said resist regionlocated at a scribing line on margin of a second substrate with colorfilter thereon; depositing a blanket passivation layer on said sourceelectrode, said drain electrode, and said resist region.
 14. The methodaccording to claim 13, wherein said resist region is formed of metal.15. The method according to claim 14, wherein said resist region isfloating.
 16. The method according to claim 15, wherein said step offormation said floating metal resist region is at a step of formation ofsaid source electrode and said drain electrode.
 17. The method accordingto claim 16, wherein formation of said floating metal resist regioncomprises: forming an island semiconductor layer on said gate insulatinglayer and over said gate electrode; depositing a blanket metal layer onsaid island semiconductor layer and said gate insulating layer;performing a lithographic process to said conductive layer by using areticle with a source pattern and a drain pattern on said gate electrodeand a resist region pattern on said gate terminal and said lead; andetching said conductive layer to form said source electrode, said drainelectrode and said floating metal resist region.
 18. The methodaccording to claim 15, wherein activity of said floating metal resistregion is less than said gate electrode line.
 19. The method accordingto claim 15, wherein distance between said scribing line and margin ofsaid floating metal resist region is about more than 50 μm.
 20. Themethod according to claim 19, wherein width of said floating metalresist region is larger than said gate terminal and said gate electrodeline.